Share Email Print

Proceedings Paper

Sensitivity study of printed wiring board plated-through-holes copper barrel voids
Author(s): Chao-Pin Yeh; Charles Umeagukwu; Robert E. Fulton; William Teat
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Improved printed wiring board (PWB) manufacturing technology has resulted in more advanced methods for component mounting (such as surface mount technology). Evidence has shown that the new generation of PWBs cannot be built using surface mount technology (SMT) alone. Some passive components and connectors can only be mounted by using plated through holes (PTHs) and vias. Up to now PTHs and vias are still the most widely used inter-layer connections in a PWB. The advanced miniaturization technologies has dramatically reduced the size of a PTH to as small as 5mils and the use of multilayer composite construction further increases the level of design complexity. It has been determined that PTH failure results from thermo-mechanical deformation due to mismatch of coefficients of thermal expansion (CTE) in the out-of-plane (Z) direction between board substrate and the PTH copper plating at elevated temperatures. Although many studies have been conducted concerning the general PTH design what has not yet been evaluated in a systematic and comprehensive manner is the PWB failure resulting from copper barrel plating voids. A collaborative research effort between Georgia Tech and Motorola has recently been carried out to investigate the influence of voids on PTH failures. This study first identifies the basic key design parameters (such as void size void shape void location copper plating thickness etc. ) relevant to void characterization. These parameters with selected values were collectively formed a

Paper Details

Date Published: 1 April 1991
PDF: 12 pages
Proc. SPIE 1389, Microelectronic Interconnects and Packages: Optical and Electrical Technologies, (1 April 1991); doi: 10.1117/12.25522
Show Author Affiliations
Chao-Pin Yeh, Georgia Institute of Technology (United States)
Charles Umeagukwu, Georgia Institute of Technology (United States)
Robert E. Fulton, Georgia Institute of Technology (United States)
William Teat, Motorola, Inc. (United States)

Published in SPIE Proceedings Vol. 1389:
Microelectronic Interconnects and Packages: Optical and Electrical Technologies
Gnanalingam Arjavalingam; James Pazaris, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?