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Proceedings Paper

A comparative analysis of EUV sheet and gate patterning for beyond 7nm gate all around stacked nanosheet FET’s (Conference Presentation)

Paper Abstract

Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet patterning as a replacement to complex double patterning schemes. While front-up sheet pitches and gate pitches expected for the beyond 7nm node fall well within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet variation requirements at technology minimum sheet widths and gate lengths. Here, we explore the crossover point between direct print EUV and optical/EUV based double patterning processes for sheets and gates in the 40 – 50 nm sheet pitch/CPP regime. We demonstrate that to enable the minimum sheet widths of <20nm required for the technology, direct bright field print with shrink results in high variability. We develop a tone invert process with darkfield sheet print that utilizes a polymerizing etch to reduce variability and achieve sub-20nm sheet widths with reduced variability, comparable to a self-aligned double patterning (SADP) process. With gate length variation requirements being tighter, we show that SADP still yields a considerable improvement in line edge/width roughness over a direct print process. We project EUV technology into the future to quantify improvements that would enable direct printed gates that match SADP. Our results will provide a guideline to down-select patterning processes for the nanosheet front end while optimizing cost and complexity.

Paper Details

Date Published: 25 March 2020
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280B (25 March 2020);
Show Author Affiliations
Indira Seshadri, IBM Corp. (United States)
Praveen Joseph, IBM Corp. (United States)
Stuart A. Sieg, IBM Corp. (United States)
Tao Li, IBM Corp. (United States)
Wenyu Xu, IBM Corp. (United States)
Eric Miller, IBM Corp. (United States)
Dan J. Dechene, IBM Corp. (United States)
Andrew Greene, IBM Corp. (United States)
Carl Radens, IBM Corp. (United States)
Jingyun Zhang, IBM Corp. (United States)
Yann Mignot, IBM Corp (United States)
Pietro Montanini, IBM Corp. (United States)
Mary Breton, IBM Corp. (United States)
Veeraraghavan Basker, IBM Corp. (United States)
Nelson Felix, IBM Corp. (United States)

Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

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