Share Email Print
cover

Proceedings Paper

Sequential 3D standard cell 4T architecture using design crenellation and self-aligned MOL for N2 technology and beyond
Author(s): Pieter Weckx; Bilal Chehab; Julien Ryckaert; Diederik Verkest; Alessio Spessot
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

As traditional pitch scaling is losing steam, 3D logic is being explored to further extend density scaling as an alternative to continued standard cell scaling. This paper will discuss standard cell architectures to be used in a Sequential 3D process where the SoC is comprised out of 2 or more tiers of active CMOS with a given BEOL metal stack per tier. Using backside interconnect metals as standard cell power rails, a smart partitioning of the metal usage within standard cells can be obtained leading to 4 track cell height scaling. A design abstraction using crenelated design is however needed at block level to mitigate via and metal line end conflicts.

Paper Details

Date Published: 23 March 2020
PDF: 6 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280A (23 March 2020);
Show Author Affiliations
Pieter Weckx, imec (Belgium)
Bilal Chehab, imec (Belgium)
Julien Ryckaert, imec (Belgium)
Diederik Verkest, imec (Belgium)
Alessio Spessot, imec (Belgium)


Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

© SPIE. Terms of Use
Back to Top
PREMIUM CONTENT
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?
close_icon_gray