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Proceedings Paper

Saving scribe-lane space by using narrow alignment marks
Author(s): Chia-Hung Chen; Sheng-Tsung Tsao; CongCong Fan; Jie Du; Richer Yang; Asei Chou
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Paper Abstract

During wafer exposure, the scanner overlays product structures from the layer being exposed onto underlying layers, with a limited error margin. Alignment is the process of measuring pre-defined marks that have been exposed on previous layers and using these measurements to determine what adjustments to make during exposure. Current alignment marks are still quite big compared to overlay targets and fill quite some reticle-area. Therefore, there is a drive towards narrower and smaller alignment marks in order to free up scribe-lane space. Further, during design of narrower and/or smaller alignment marks, not only the width or length needs to be taken into account, but also the process loading effect and scribe-lane dummy following rules.

Maximizing product-area is an important driver for many DRAM customers. One way is by reducing scribe-lane space. Currently most customers are using 60um to 90 um wide scribe-lanes. However, developments are ongoing to further reduce this to 40um -50um. The current narrowest standard ASML alignment marks are 40 um wide and there is a growing demand for narrower and even smaller marks. Experiment tool groups configure selection with ASML SMASH senor and it brings more possibility in scribe-lane design and alignment size topic.

Tests with narrow alignment marks were done on an ASML XT1460K scanner with SMASH3.1 sensor. Both narrow DPCM (coarse align) and narrow NSSM marks (coarse and fine align) were tested and the impact on accuracy, repro and overlay was investigated. The width of the DPCM marks was reduced from 160um to 150um and 140um. The width of the NSSM (AA11 and AH53) marks was reduced from 40um to 30um and 28um.

This paper will explain the tests done in detail and will present the results of using narrow marks on alignment mark repro, mark KPIs (WQ, MCC, etc.) and overlay performance. These results will be compared to those of the standard marks. Also results from further alignment mark recipe optimization will be presented.

Paper Details

Date Published: 20 March 2020
PDF: 7 pages
Proc. SPIE 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV, 113252V (20 March 2020);
Show Author Affiliations
Chia-Hung Chen, Changxin Memory Technology Co., Ltd. (China)
Sheng-Tsung Tsao, Changxin Memory Technology Co., Ltd. (China)
CongCong Fan, Changxin Memory Technology Co., Ltd. (China)
Jie Du, Changxin Memory Technology Co., Ltd. (China)
Richer Yang, Changxin Memory Technology Co., Ltd. (China)
Asei Chou, ChangXin Memory Technology Co., Ltd. (China)


Published in SPIE Proceedings Vol. 11325:
Metrology, Inspection, and Process Control for Microlithography XXXIV
Ofer Adan; John C. Robinson, Editor(s)

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