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Proceedings Paper

Enabling nanoimprint simulator for quality verification; process-design co-optimization toward high volume manufacturing
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Paper Abstract

Computational technologies are still in the course of development for nanoimprint lithography (NIL). Only a few simulators are applicable to the nanoimprint process, and these simulators are desired by device manufacturers as part of their daily toolbox. The most challenging issue in NIL process simulation is the scale difference of each component of the system. The template pattern depth and the residual resist film thickness are generally of the order of a few tens of nanometers, while the process needs to work over the entire shot size, which is typically of the order of 10 mm square. This amounts to a scale difference of the order of 106. Therefore, in order to calculate the nanoimprint process with conventional fluid structure interaction (FSI) simulators, an enormous number of meshes is required, which results in computation times that are unacceptable. In this paper, we introduce a new process simulator which directly inputs the process parameters, simulates the whole imprinting process, and evaluates the quality of the resulting resist film. To overcome the scale differences, our simulator utilizes analytically integrated expressions which reduce the dimensions of the calculation region. In addition, the simulator can independently consider the positions of the droplets and calculate the droplet coalescence, thereby predicting the distribution of the non-fill areas which originate from the trapped gas between the droplets. The simulator has been applied to the actual NIL system and some examples of its applications are presented here.

Paper Details

Date Published: 23 March 2020
PDF: 12 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280N (23 March 2020);
Show Author Affiliations
Junichi Seki, Canon Inc. (Japan)
Yuichiro Oguchi, Canon Inc. (Japan)
Naoki Kiyohara, Canon Inc. (Japan)
Koshiro Suzuki, Canon Inc. (Japan)
Kohei Nagane, Canon Inc. (Japan)
Shintaro Narioka, Canon Inc. (Japan)
Takahiro Nakayama, Canon Inc. (Japan)
Yoshihiro Shiode, Canon Inc. (Japan)
Sentaro Aihara, Canon Inc. (Japan)
Toshiya Asano, Canon Inc. (Japan)


Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

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