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Proceedings Paper

Understanding advanced DRAM edge placement error budget and opportunities for control
Author(s): Jaeseung Jeong; Jinho Lee; Jinsun Kim; Sunyoung Yea; Chan Hwang; Seung Yoon Lee; Jeongjin Lee; Joonsoo Park; Peter Nikolsky; Daniel Park; Antonio Corradi; Hyun-Woo Yu; Sun-Wook Jung; Denis Ovchinnikov; Vadim Timoshkov; Isabel de la Fuente Valentin; Yuxiang Yin; Kaustubh Padhye; Wim Tel; Harm Dillen; Koen Thuijs; Daan Slotboom; Miao Wang; Rhys Su; Marc Kea; Jin-Woo Lee; Yun-A Sung; Sang-Uk Kim; Young-Hoon Song; James Lee; Oh-Sung Kwon
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Paper Abstract

In leading edge patterning processes, overlay is now entangled with CD including OPC residuals and stochastics. This combined effect is a serious challenge for continued shrink and can be characterized with an Edge Placement Error (EPE) budget containing multi-domain components: global and local CD, local placement errors, overlay errors, etch biases and OPC. EPE defines process capability and ultimately relates to device yield. Understanding the EPE budget leads to efficient ways to monitor process capability and optimize it using EPE based process control applications. We examine a critical EPE use case on a leading edge DRAM node. We start by constructing and verifying the EPE Budget via densely sampled on-product in-device local, global CD and Overlay metrology after the etch process step. EPE budget contributors are ranked according to their impact to overall EPE performance and later with simulated EPE performance improvements per component. A cost/benefit analysis is shown to help choose the most HVM-friendly solutions.

Paper Details

Date Published: 20 March 2020
PDF: 8 pages
Proc. SPIE 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV, 1132506 (20 March 2020);
Show Author Affiliations
Jaeseung Jeong, Samsung Electronics Co., Ltd. (Korea, Republic of)
Jinho Lee, Samsung Electronics Co., Ltd. (Korea, Republic of)
Jinsun Kim, Samsung Electronics Co., Ltd. (Korea, Republic of)
Sunyoung Yea, Samsung Electronics Co., Ltd. (Korea, Republic of)
Chan Hwang, Samsung Electronics Co., Ltd. (Korea, Republic of)
Seung Yoon Lee, Samsung Electronics Co., Ltd. (Korea, Republic of)
Jeongjin Lee, Samsung Electronics Co., Ltd. (Korea, Republic of)
Joonsoo Park, Samsung Electronics Co., Ltd. (Korea, Republic of)
Peter Nikolsky, ASML Netherlands B.V. (Netherlands)
Daniel Park, ASML Netherlands B.V. (Netherlands)
Antonio Corradi, ASML Netherlands B.V. (Netherlands)
Hyun-Woo Yu, ASML Netherlands B.V (Netherlands)
Sun-Wook Jung, ASML Netherlands B.V. (Netherlands)
Denis Ovchinnikov, ASML Netherlands B.V. (Netherlands)
Vadim Timoshkov, ASML Netherlands B.V. (Netherlands)
Isabel de la Fuente Valentin, ASML Netherlands B.V. (Netherlands)
Yuxiang Yin, ASML Netherlands B.V. (Netherlands)
Kaustubh Padhye, ASML Netherlands B.V. (Netherlands)
Wim Tel, ASML Netherlands B.V. (Netherlands)
Harm Dillen, ASML Netherlands B.V. (Netherlands)
Koen Thuijs, ASML Netherlands B.V. (Netherlands)
Daan Slotboom, ASML Netherlands B.V. (Netherlands)
Miao Wang, ASML Netherlands B.V. (Netherlands)
Rhys Su, ASML Netherlands B.V. (Netherlands)
Marc Kea, ASML Netherlands B.V. (Netherlands)
Jin-Woo Lee, ASML Netherlands B.V. (Netherlands)
Yun-A Sung, ASML Netherlands B.V. (Netherlands)
Sang-Uk Kim, ASML Netherlands B.V. (Netherlands)
Young-Hoon Song, ASML Netherlands B.V. (Netherlands)
James Lee, ASML Netherlands B.V. (Netherlands)
Oh-Sung Kwon, ASML Netherlands B.V. (Netherlands)


Published in SPIE Proceedings Vol. 11325:
Metrology, Inspection, and Process Control for Microlithography XXXIV
Ofer Adan; John C. Robinson, Editor(s)

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