Share Email Print
cover

Proceedings Paper

Nanoimprint system alignment and overlay improvement for high volume semiconductor manufacturing
Author(s): Atsushi Kimura; Yukio Takabayashi; Takehiko Iwanaga; Mitsuru Hiura; Keita Sakai; Hiroshi Morohoshi; Toshiya Asano; Tatsuya Hayashi; Takamitsu Komaki
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, improvements to the alignment system, together with the High Order Distortion Correction (HODC) system have enabled better distortion and overlay results. On test wafers, XMMO of 3.2nm and 2.8nm in x and y respectively was demonstrated. There is also an opportunity to further improve results by applying wafer chucks with better flatness specifications. Further advances have also been made through the application of a multi-wavelength alignment strategy. Finally, we discuss how computational methods can enhance NIL productivity and reduce the number of learning cycles

Paper Details

Date Published: 23 March 2020
PDF: 9 pages
Proc. SPIE 11324, Novel Patterning Technologies for Semiconductors, MEMS/NEMS and MOEMS 2020, 113240B (23 March 2020); doi: 10.1117/12.2551985
Show Author Affiliations
Atsushi Kimura, Canon Inc. (Japan)
Yukio Takabayashi, Canon Inc. (Japan)
Takehiko Iwanaga, Canon Inc. (Japan)
Mitsuru Hiura, Canon Inc. (Japan)
Keita Sakai, Canon Inc. (Japan)
Hiroshi Morohoshi, Canon Inc. (Japan)
Toshiya Asano, Canon Inc. (Japan)
Tatsuya Hayashi, Canon Inc. (Japan)
Takamitsu Komaki, Canon Inc. (Japan)


Published in SPIE Proceedings Vol. 11324:
Novel Patterning Technologies for Semiconductors, MEMS/NEMS and MOEMS 2020
Martha I. Sanchez; Eric M. Panning, Editor(s)

© SPIE. Terms of Use
Back to Top
PREMIUM CONTENT
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?
close_icon_gray