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Proceedings Paper

Process related yield risk mitigation with in-design pattern replacement for system ICs manufactured at advanced technology nodes
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Paper Abstract

Process and reliability risks have become critically important during mass production at advanced technology nodes even with Extreme Ultraviolet Lithography (EUV) illumination. In this work, we propose a design-for-manufacturability solution using a set of new rules to detect high risk design layout patterns. The proposed methods improve design margins while avoiding area overhead and complex design restrictions. In addition, the proposed method introduces an in-design pattern replacement with automatically generated fixing hints to improve all matched locations with identified patterns.

Paper Details

Date Published: 23 March 2020
PDF: 8 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280I (23 March 2020); doi: 10.1117/12.2551970
Show Author Affiliations
Jaehwan Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Jin Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Byungchul Shin, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Sangah Lee, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Jae-Hyun Kang, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Joong-Won Jeon, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Piyush Pathak, Cadence Design Systems, Inc. (United States)
Jac Condella, Cadence Design Systems, Inc. (United States)
Frank E. Gennari, Cadence Design Systems, Inc. (United States)
Philippe Hurat, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

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