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Proceedings Paper

Co-optimizing DFM enhancements and their impact on layout-induced circuit performance for analog designs
Author(s): Lynn Wang; Michael Simcoe; Vikas Mehrotra; Gail Katzman; Rais Huda; Zhao Chuan Lee; Janam Bakshi; Ahmed Abdulghany; Uwe Paul Schroeder; Sriram Madhavan
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Paper Abstract

A symmetry-aware DFM layout insertion flow for matched circuits is developed for enhancing analog and mixed-signal designs. Pattern capture is used to categorize the matched circuits to unique groups of layout patterns and store them in a pattern database, in which each pattern has an associated group identification, a match location, a region of extent, and a symmetry constraint. Using the stored information in the pattern database, DFM layout insertions are applied to the base pattern and replicated for the symmetric patterns to generate an optimized layout, thus preserving the original symmetry. The impact of the DFM insertions on analog circuit performance was quantified using electronic simulators. The application of symmetry-aware DFM enhancements to analog designs achieves nearly 100% DFM compliance with negligible 0.1-0.2% impact to analog electrical parameters.

Paper Details

Date Published: 23 March 2020
PDF: 9 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280M (23 March 2020);
Show Author Affiliations
Lynn Wang, GLOBALFOUNDRIES Inc. (United States)
Michael Simcoe, GLOBALFOUNDRIES Inc. (United States)
Vikas Mehrotra, GLOBALFOUNDRIES Inc. (United States)
Gail Katzman, GLOBALFOUNDRIES Inc. (United States)
Rais Huda, GLOBALFOUNDRIES Inc. (United States)
Zhao Chuan Lee, GLOBALFOUNDRIES Inc. (United States)
Janam Bakshi, GLOBALFOUNDRIES Inc. (United States)
Ahmed Abdulghany, GLOBALFOUNDRIES Inc. (United States)
Uwe Paul Schroeder, GLOBALFOUNDRIES Inc. (United States)
Sriram Madhavan, GLOBALFOUNDRIES Inc. (United States)


Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

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