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Proceedings Paper

Via optimization methodology for enhancing robustness of design at 14/12nm technology node
Author(s): Xiaojing Su; Libin Zhang; Yayi Wei; Rui Chen; Yajuan Su; Lisong Dong; Chunshan Du; Qijian Wan; Xinyi Hu
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Paper Abstract

Via location and metal coverage have direct correlation. Optical proximity correction (OPC) always do selective sizing for metal to offer enough via enclosure, such as extending line end or doing external expansion for related metal edge. Hence via poor landing or metal bridging are both potential hotspots. For 14nm technology node and below, process related weak patterns are highly correlated with via locations and corresponding metal dimensions. A via optimization methodology has been put forward to enhance the robustness of design for physical design in fabless. With the aid of lithography check, the yield killers with high potential relativity with vias will be conducted root cause analysis. This paper describes the main solutions for fabless, including pin location blockage, via shift, via shape change, metal sizing change and so on within design rule check (DRC) constraints. The simulation experiment results prove the effective of these solutions due to related simulated yield killers being eliminated.

Paper Details

Date Published: 23 March 2020
PDF: 9 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 1132810 (23 March 2020); doi: 10.1117/12.2551902
Show Author Affiliations
Xiaojing Su, Institute of Microelectronics (China)
Univ. of Chinese Academy of Sciences (China)
Libin Zhang, Institute of Microelectronics (China)
Yayi Wei, Institute of Microelectronics (China)
Univ. of Chinese Academy of Sciences (China)
Rui Chen, Institute of Microelectronics (China)
Yajuan Su, Institute of Microelectronics (China)
Lisong Dong, Institute of Microelectronics (China)
Chunshan Du, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Qijian Wan, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Xinyi Hu, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)

Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

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