Share Email Print
cover

Proceedings Paper

Systematic DTCO flow for yield improvement at 14/12nm technology node
Author(s): Xiaojing Su; Yayi Wei; Rui Chen; Yajuan Su; Lisong Dong; Joe Kwan; Recoo Zhang; Chunshan Du; Qijian Wan; Xinyi Hu
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Design technology co-optimization (DTCO) is one of the most critical considerations for yield breakthrough and product ramp-up during the life cycle of a new technology node. Traditional sign-off flow of physical verification cannot guarantee manufacturability totally. Comprehensive design for manufacturing (DFM) check should be involved in flow of product tape-out in order to recognize the patterning and other process challenges which would limit the wafer yield. The process related hotspots were pre-defined with the aid of process related simulation kits on cell, block as well as full chip levels. A systematic DTCO methodology including fabless process friendly flow with lithography friendly design (LFD), pattern match and chemical mechanical planarization (CMP) check, resolution enhancement technology (RET) synthesis, process window check for sensitive patterns as well as weak pattern library assisted circuit diagnosis was as an example of DTCO application at 14/12nm in this paper.

Paper Details

Date Published: 23 March 2020
PDF: 11 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280L (23 March 2020);
Show Author Affiliations
Xiaojing Su, Institute of Microelectronics (China)
Univ. of Chinese Academy of Sciences (China)
Yayi Wei, Institute of Microelectronics (China)
Univ. of Chinese Academy of Sciences (China)
Rui Chen, Institute of Microelectronics (China)
Yajuan Su, Institute of Microelectronics (China)
Lisong Dong, Institute of Microelectronics (China)
Joe Kwan, Mentor, a Siemens Business (United States)
Recoo Zhang, Mentor, a Siemens Business (United States)
Chunshan Du, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Qijian Wan, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Xinyi Hu, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)


Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

© SPIE. Terms of Use
Back to Top
PREMIUM CONTENT
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?
close_icon_gray