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Proceedings Paper

Reduction of systematic defects with machine learning from design to fab
Author(s): Yuansheng Ma; Le Hong; James Word; Fan Jiang; Vlad Liubich; Liang Cao; Srividya Jayaram; Doohwan Kwak; YoungChang Kim; Germain Fenger; Ananthan Raghunathan; Joerg Mellmann
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Paper Abstract

Maximizing yield in a modern semiconductor fab requires proper optimization of the design (layout), process technology, and fab process tool recipes. For the past decade the prevalence of systematic defects tied to design or design-process interactions have predominated over random defect sources. Previously Resolution Enhancement Technology (RET), Design For Manufacturability (DFM), and Design-Technology Co-optimization (DTCO) techniques were the successful response to eliminating systematic yield limiting patterns. Machine learning, with its ability to find trends and make predictions based on large volumes of data, provides a unique path towards further reduction in systematic defect levels. This talk will present methods based on the use of design and process info with machine learning and computational lithography methods to identify and eliminate yield limiting patterns in the design, improve the accuracy of mask generation with etch and resist modeling and OPC, and improve the productivity and accuracy of fab defect detection and diagnostics. This paper will present methods to improve EPE control and reduce systematic hotspots through both supervised and unsupervised machine learning. Specifically we will focus on 3 areas: - identifying and yield limiting patterns in the design phase. - improving the accuracy (EPE control) of mask generation with machine learning assisted etch and resist modeling and OPC. - improving the productivity and accuracy of fab defect detection and diagnostics with machine learning.

Paper Details

Date Published: 23 March 2020
PDF: 14 pages
Proc. SPIE 11329, Advanced Etch Technology for Nanopatterning IX, 1132909 (23 March 2020); doi: 10.1117/12.2551703
Show Author Affiliations
Yuansheng Ma, Mentor Graphics Corp. (United States)
Le Hong, Mentor Graphics Corp. (United States)
James Word, Mentor Graphics Corp. (United States)
Fan Jiang, Mentor Graphics Corp. (United States)
Vlad Liubich, Mentor Graphics Corp. (United States)
Liang Cao, Mentor Graphics Corp. (United States)
Srividya Jayaram, Mentor Graphics Corp. (United States)
Doohwan Kwak, Mentor Graphics Korea LLC. (Korea, Republic of)
YoungChang Kim, Mentor Graphics Corp. (United States)
Germain Fenger, Mentor Graphics Corp. (United States)
Ananthan Raghunathan, Mentor Graphics Corp. (United States)
Joerg Mellmann, Mentor Graphics Corp. (United States)

Published in SPIE Proceedings Vol. 11329:
Advanced Etch Technology for Nanopatterning IX
Richard S. Wise; Catherine B. Labelle, Editor(s)

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