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Proceedings Paper

VIA design optimization for fast yield ramping in advanced nodes
Author(s): Min Wang; Yizhong Zhang; Shirui Yu; Xinyi Hu; Qijian Wan; Zhengfang Liu; Zhixi Chen; Chunshan Du
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Paper Abstract

High yield is always demanded in IC manufacturing, however, as process variations and random particles are part of the manufacturing process in nature, yield and circuit performance are inevitably impacted by these factors especially in advanced nodes. Even so, there’s often some room to polish designs to be manufacturing friendly. The design for manufacturability (DFM) approach has been taken to optimize designs to minimize process variation impact on the yield and performance. One area gaining success toward yield improvement is VIA (Vertical Interconnect Access) design optimization. There are some technical approaches that designers may take: adding redundant VIA at possible spots without increasing the design area is a proven way to address random particle induced VIA void issues; increasing VIA enclosure area by shifting VIA to an optimum location effectively minimizes masks misalignment induced enclosure issues, and note that shifting VIA needs to consider some complex situations when clustered VIAs constrain each other. There are also other circumstances that need to be considered and handled depending on specific manufacturing process. All these contents will be presented in detail in the paper.

Paper Details

Date Published: 23 March 2020
PDF: 4 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 1132814 (23 March 2020); doi: 10.1117/12.2551683
Show Author Affiliations
Min Wang, Shanghai Huali Integrated Circuit Corp. (China)
Yizhong Zhang, Shanghai Huali Integrated Circuit Corp. (China)
Shirui Yu, Shanghai Huali Integrated Circuit Corp. (China)
Xinyi Hu, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Qijian Wan, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Zhengfang Liu, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Zhixi Chen, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Chunshan Du, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)

Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

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