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Proceedings Paper

An efficient way to accelerate litho hotspot checking
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Paper Abstract

It’s desirable to gain high yield and good performance for memory products. Designers have to do some advanced DFM checking on their designs and fix all the critical design issues to be correct by construction before manufacturing. One of the DFM checking items is the litho hotspot checking, LFD (Litho Friendly Design) is the tool adopted for that checking due to its user friendly interface for designers and being able to be integrated with other tools for the advanced checking flow development. One challenge to enable this checking as the signoff item is the long runtime due to the computing-intensive litho simulation. Multiple ways have been figured out to reduce the runtime, for instance, hierarchical checking flow similar to hierarchical design flow under the assumption that many design blocks are reused on the top level; simulation only on the area selected by weak pattern candidates stored in a pattern matching library; simulation only on the unique pattern area by firstly decomposing the layout. All these approaches always tradeoff between runtime and simulation accuracy and come to use with different expectations as the process gradually matures. This paper introduces another technique to reduce the simulation time. This technique is essentially a pattern matching extended application and will be introduced in detail in the paper.

Paper Details

Date Published: 23 March 2020
PDF: 6 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 1132818 (23 March 2020);
Show Author Affiliations
Jet Jiang, Yangtze Memory Technologies Co., Ltd. (China)
Gavin Li, Yangtze Memory Technologies Co., Ltd. (China)
Frank Hou, Yangtze Memory Technologies Co., Ltd. (China)
Qijian Wan, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Xinyi Hu, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Zhengfang Liu, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Zhixi Chen, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Chunshan Du, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)

Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

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