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Proceedings Paper

CMP simulation-based dummy fill optimization
Author(s): Liwei Jiang; Yun Cao; Jiao Zhang; Fang Wei; Zhengfang Liu; Chunshan Du; Ruben Ghulghazaryan; Davit Piliposyan; Jeff Wilson; Qijian Wan; Xinyi Hu; Zhixi Chen
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Paper Abstract

Chemical-mechanical polishing (CMP) is a key process in integrated circuit (IC) manufacturing. Successful fabrication of semiconductor devices is highly dependent on the final planarity of the processed layers. Post-CMP topography variation may cause degradation of the circuit performance. Moreover, the depth-of-focus (DOF) requirement is critical for lithography of subsequent layers. As such, planarity requirements are critical for maintaining IC manufacturing technology scaling trends, and supporting device innovation. To mitigate post-CMP planarity issues, dummy fill insertion has become a commonly-used technique. Many factors impact dummy fill insertion results, including fill shapes, sizes, and the spacing between both fill shapes and the drawn layout patterns. The goal of the CMP engineer is to optimize design planarity, but the variety of fill options means just verifying the design rules for fill is a challenging task. This data collection currently requires a long development cycle, consuming a great deal of time and resources. In this paper, we show how CMP modeling can help resolve these issues by applying CMP modeling and simulations to drive Calibre YieldEnhancer SmartFill parameters that have been optimized for dummy fill. Additional capabilities in the SmartFill functionality automate CMP hotspot fixing steps. Using CMP simulations, engineers can get feedback about post-CMP planarity for given fill options in a much shorter time. Not only does this move dummy fill optimization experiments from a real lab into a virtual lab of CMP modeling and simulation, but it also provides more time for these experiments, providing improved results.

Paper Details

Date Published: 23 March 2020
PDF: 9 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 1132817 (23 March 2020); doi: 10.1117/12.2551681
Show Author Affiliations
Liwei Jiang, Shanghai Huali Microelectronics Corp. (China)
Yun Cao, Shanghai Huali Microelectronics Corp. (China)
Jiao Zhang, Shanghai Huali Microelectronics Corp. (China)
Fang Wei, Shanghai Huali Microelectronics Corp. (China)
Zhengfang Liu, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Chunshan Du, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Ruben Ghulghazaryan, Mentor Graphics Corp. (Armenia)
Davit Piliposyan, Mentor Graphics Corp. (Armenia)
Jeff Wilson, Mentor, a Siemens Business (United States)
Qijian Wan, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Xinyi Hu, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Zhixi Chen, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)

Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

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