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Proceedings Paper

A comprehensive standard cell library qualification to prevent lithographic challenges
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Paper Abstract

Standard cells are the most critical and reusable elements to build up the whole chip, therefore foundry has to fully qualify the standard cell libraries to ensure their high quality when releasing to the customers for the chip design. To prevent pattern dependent lithographic difficulty in manufacturing is one target of standard cell qualification and becomes mandatory especially in advanced nodes due to tighter design rules and smaller design size. To identify a lithographic problematic standard cell, we have to take its surroundings within the optical diameter range into consideration because lithographic effects are intrinsically context-dependent. One critical step is to imitate standard cells placements in real designs and consider some important factors like VIA location as it impacts the mask shape directly. When the placement is completed, lithographic simulation is performed by LFD (Litho Friendly Design) to highlight risky locations. Every standard cell has to occur enough number of times to make sure the statistics of possibility of being a problem is reliable. The final statistics will instruct engineers on how to handle the problematic standard cells, either standard cell layouts have to be optimized or building a pattern database to prevent the abutments of particular standard cell combinations.

Paper Details

Date Published: 23 March 2020
PDF: 5 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113281C (23 March 2020); doi: 10.1117/12.2551677
Show Author Affiliations
Xinyi Hu, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Qijian Wan, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Zhengfang Liu, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Zhixi Chen, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Chunshan Du, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)

Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

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