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Proceedings Paper

DFM: “Design for Manufacturing” or “Design Friendly Manufacturing” How to convert extra EPE budget into design freedom by SMO
Author(s): Wenzhan Zhou; Hung-Wen Chao; Yu Zhang; Chan-Yuan Hu; QiXin Xu; Quan Gan; Ao Chen; Gen-Sheng Gao
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Paper Abstract

As the IC manufacturing enter sub 20nm tech nodes, DFM become more and more important to make sure more stable yield and lower cost. However, by introducing newly designed hardware (1980i etc) process chemical (NTD) and Control Algorithm (Focus APC) into the mature tech nodes such as 14nm/12nm, more process window and less process variations are expected for latecomer wafer fabs (Tier-2/3 companies) who just started the competition with Tier-1 companies. With improved weapons, latecomer companies are able to review their DFM strategy one more time to see whether the benefit from hardware/process/control algorithm improvement can be shared with designers In this paper, we use OPC simulation tools from different EDA suppliers to see the feasibility of transferring the benefits of hardware/process/control algorithm improvement to more relaxed design limitation through source mask optimization (SMO): 1) Better hardware: scanner (better focus/exposure variation), CMP (intrafield topo), Mask CD variation (relaxed MEEF spec), etc.; 2) New process: from positive tone development to negative tone development; 3) Better control schemes: holistic focus feedback, feedback/forward overlay control, high order CD uniformity improvement; Simulations show all those gains in hardware and process can be transferred into more relaxed design such as sub design rule structure process window include forbidden pitches (1D) and smaller E2E gaps (2D weak points).

Paper Details

Date Published: 23 March 2020
PDF: 10 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113281A (23 March 2020);
Show Author Affiliations
Wenzhan Zhou, Shanghai Huali Integrated Circuit Corp. (China)
Hung-Wen Chao, Shanghai Huali Integrated Circuit Corp. (China)
Yu Zhang, Shanghai Huali Integrated Circuit Corp. (China)
Chan-Yuan Hu, Shanghai Huali Integrated Circuit Corp. (China)
QiXin Xu, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Quan Gan, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Ao Chen, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)
Gen-Sheng Gao, Mentor Graphics (Shanghai) Electronics Technology Co., Ltd. (China)

Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

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