Share Email Print
cover

Proceedings Paper

Early detection of Cu pooling with advanced CMP modeling
Author(s): Single Hsu; Ethan Wang; Eason Lin; Tamba Gbondo-Tugbawa; Aaron Gower-Hall; Brian Lee; Jansen Chee; Ya-Chieh Lai
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

As we move to more advanced nodes, the number of Chemical Mechanical Polishing (CMP) steps in semiconductor processing is increasing rapidly. CMP is known to suffer from pattern dependent variation such as dishing, erosion, recess, etc., all of which can cause performance and yield issues. One such yield issue seen in back end of line (BEOL) Cu interconnect CMP processes is pooling. Pooling exists when there is uncleared bulk Cu and/or barrier residue remaining after final CMP step, leading to shorts between neighboring interconnect lines. To detect potential pooling locations on a given design, for a given CMP process, predictive CMP models are needed. Such models can also aid in CMP process and chip design optimizations. In this paper we discuss how a pattern dependent CMP effect that we call the “local neighborhood effect” causes large recesses that can lead to pooling in Cu interconnect CMP processes. We also discuss modeling this effect as part of an advanced predictive CMP modeling system and show how the resulting modeling system accurately predicts Cu pooling on several 14 nm designs.

Paper Details

Date Published: 23 March 2020
PDF: 5 pages
Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 1132816 (23 March 2020);
Show Author Affiliations
Single Hsu, United Microelectronics Corp. (Taiwan)
Ethan Wang, Cadence Design Systems, Inc. (Taiwan)
Eason Lin, Cadence Design Systems, Inc. (Taiwan)
Tamba Gbondo-Tugbawa, Cadence Design Systems, Inc. (United States)
Aaron Gower-Hall, Cadence Design Systems, Inc. (United States)
Brian Lee, Cadence Design Systems, Inc. (United States)
Jansen Chee, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 11328:
Design-Process-Technology Co-optimization for Manufacturability XIV
Chi-Min Yuan, Editor(s)

© SPIE. Terms of Use
Back to Top
PREMIUM CONTENT
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?
close_icon_gray