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Proceedings Paper

Design considerations for multi-chip module silicon-photonic transceivers
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Paper Abstract

High bandwidth density silicon photonic interconnects offer the potential to address the massive increase in bandwidth demands for data center traffic and high performance computing. One of the major challenges in realizing silicon photonics transceivers is the integration and packing of photonic ICs (PIC) with electronic ICs (EIC). This paper presents our version one, 2.5D integrated multi-chip module (MCM) transceiver for 4 channel wavelength division multiplexing (WDM) operation, targeting 10 Gbps per channel. We identify five key areas critical to successful integration of MCM transceivers, which we have used in developing our version two MCM transceiver: integration architecture, equivalent circuit model development, PIC to EIC interface modelling, MCM I/O design, and design for assembly.

Paper Details

Date Published: 31 January 2020
PDF: 11 pages
Proc. SPIE 11308, Metro and Data Center Optical Networks and Short-Reach Links III, 113080I (31 January 2020); doi: 10.1117/12.2544008
Show Author Affiliations
Nathan C. Abrams, Columbia Univ. (United States)
Qixiang Cheng, Columbia Univ. (United States)
Madeleine Glick, Columbia Univ. (United States)
Evgeny Manzhosov, Columbia Univ. (United States)
Moises Jezzini, Tyndall National Institute (Ireland)
Padraic Morrissey, Tyndall National Institute (Ireland)
Peter O'Brien, Tyndall National Institute (Ireland)
Keren Bergman, Columbia Univ. (United States)

Published in SPIE Proceedings Vol. 11308:
Metro and Data Center Optical Networks and Short-Reach Links III
Atul K. Srivastava; Madeleine Glick; Youichi Akasaka, Editor(s)

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