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Proceedings Paper

28 Gbps silicon-germanium hetero-structure avalanche photodetectors
Author(s): Daniel Benedikovic; Léopold Virot; Guy Aubin; Jean-Michel Hartmann; Farah Amar; Bertrand Szelag; Xavier Le Roux; Carlos Alonso-Ramos; Paul Crozat; Eric Cassan; Delphine Marris-Morini; Charles Baudot; Frédéric Boeuf; Jean-Marc Fédéli; Christophe Kopp; Laurent Vivien
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Paper Abstract

Owing to its low-cost, high-yield, and dense integration ability, silicon nanophotonics is a good candidate to tackle the needs of exponentially growing communications in data centers, high-performance computers, and cloud services. Moreover, a number of nanophotonic functions are now available on a single chip, as they take advantages of silicon-foundry process maturity and epitaxial germanium integration. Optical photodetectors are key building blocks in the library of group-IV components and their performances are quite successful nowadays. In particular, silicon-germanium waveguide-integrated photodetectors are fixing new standards for next generation of on-chip interconnects in terms of compactness, speed, power consumption and cost. Indeed, conventional pin photodetectors yield good responsivities (~1 A/W in a 1.5 μm wavelength range), high bandwidths (~50 GHz), and dark currents well below 1 μA. Despite recent advances, their optical power sensitivities remain rather modest and speeds are limited to 25 Gbps only, however. Compensating for the insufficient photodetector sensitivity requires higher transmitter output powers and therefore higher energy consumption. Additional energy savings can be obtained by eliminating receiver electronics. Alternatively, an appealing approach is to exploit device structures with an internal multiplication gain to lower even more the power budget and improve energy efficiency of chip-based optical links. In this work, we report on waveguide-integrated photodetectors with lateral silicon-germanium-silicon heterojunctions. Here, we present avalanche photodetectors fabricated on 200-mm silicon-on-insulator wafers using complementary metal-oxide-semiconductor-compatible processes. Devices operate in the low-gain-regime to facilitate high-speed link operations at 1.55 μm wavelengths. An error-free signal detection was achieved at 28 Gbps, with power sensitivity of -11 dBm for 10-9 bit-error-rate, which is a relevant link rate for emerging chip-scale optical interconnects.

Paper Details

Date Published: 25 February 2020
PDF: 10 pages
Proc. SPIE 11283, Integrated Optics: Devices, Materials, and Technologies XXIV, 112830Y (25 February 2020); doi: 10.1117/12.2543499
Show Author Affiliations
Daniel Benedikovic, Ctr. de Nanosciences et de Nanotechnologies, CNRS, Univ. Paris-Saclay (France)
Léopold Virot, Univ. Grenoble Alpes (France)
CEA-LETI (France)
Guy Aubin, Ctr. de Nanosciences et de Nanotechnologies, CNRS, Univ. Paris-Saclay (France)
Jean-Michel Hartmann, Univ. Grenoble Alpes (France)
CEA-LETI (France)
Farah Amar, Ctr. de Nanosciences et de Nanotechnologies, CNRS, Univ. Paris-Saclay (France)
Bertrand Szelag, Univ. Grenoble Alpes (France)
CEA-LETI (France)
Xavier Le Roux, Ctr. de Nanosciences et de Nanotechnologies, CNRS, Univ. Paris-Saclay (France)
Carlos Alonso-Ramos, Ctr. de Nanosciences et de Nanotechnologies, CNRS, Univ. Paris-Saclay (France)
Paul Crozat, Ctr. de Nanosciences et de Nanotechnologies, CNRS, Univ. Paris-Saclay (France)
Eric Cassan, Ctr. de Nanosciences et de Nanotechnologies, CNRS, Univ. Paris-Saclay (France)
Delphine Marris-Morini, Ctr. de Nanosciences et de Nanotechnologies, CNRS, Univ. Paris-Saclay (France)
Charles Baudot, STMicroelectronics S.A. (France)
Frédéric Boeuf, STMicroelectronics S.A. (France)
Jean-Marc Fédéli, Univ. Grenoble Alpes (France)
CEA-LETI (France)
Christophe Kopp, Univ. Grenoble Alpes (France)
CEA-LETI (France)
Laurent Vivien, Ctr. de Nanosciences et de Nanotechnologies, CNRS, Univ. Paris-Saclay (France)


Published in SPIE Proceedings Vol. 11283:
Integrated Optics: Devices, Materials, and Technologies XXIV
Sonia M. García-Blanco; Pavel Cheben, Editor(s)

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