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Proceedings Paper

IPbus bus functional model in universal VHDL verification methodology
Author(s): Michał Kruszewski
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Paper Abstract

Simulation-based functional verification is an important part of a Field-Programmable Gate Array (FPGA) design flow. It is desirable of test bench to be written quickly, with high abstraction and in understandable way. The paper describes IPbus Bus Functional Model (BFM) that has been implemented in the Universal VHDL Verification Methodology (UVVM) test bench infrastructure. It also presents a simple example how the module should be used.

Paper Details

Date Published: 6 November 2019
PDF: 6 pages
Proc. SPIE 11176, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2019, 1117644 (6 November 2019); doi: 10.1117/12.2536696
Show Author Affiliations
Michał Kruszewski, Warsaw Univ. of Technology (Poland)


Published in SPIE Proceedings Vol. 11176:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2019
Ryszard S. Romaniuk; Maciej Linczuk, Editor(s)

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