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Proceedings Paper

Automatic management of local bus address space in complex FPGA-implemented hierarchical systems
Author(s): Wojciech M. Zabołotny; Marek Gumiński; Michał Kruszewski
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Paper Abstract

The FPGA-implemented data acquisition and processing systems are usually configured via local bus providing access to internal control and status registers. Management of the address space of that local bus is a well known and non-trivial problem, especially in complex hierarchical systems. Even though various solutions have been already proposed, it seems that there is still a need for an open, portable address management system, capable of operation with different local bus technologies and various control interfaces. This paper presents a proposition for such a system. The multi-level hierarchy of nested blocks with internal control and status registers is supported. The blocks and registers may be implemented as single instances or vectors of multiple instances. The structure of the system is described with the XML file. The generated address map may be stored in various formats compatible with different control interfaces (e.g., IPbus or AXI). The proposed solution is compatible with the design flow based on parametrized high-level HDL implementation of the FPGA firmware.

Paper Details

Date Published: 6 November 2019
PDF: 8 pages
Proc. SPIE 11176, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2019, 1117642 (6 November 2019); doi: 10.1117/12.2536259
Show Author Affiliations
Wojciech M. Zabołotny, Warsaw Univ. of Technology (Poland)
Marek Gumiński, Warsaw Univ. of Technology (Poland)
Michał Kruszewski, Warsaw Univ. of Technology (Poland)

Published in SPIE Proceedings Vol. 11176:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2019
Ryszard S. Romaniuk; Maciej Linczuk, Editor(s)

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