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Patterning, mask life, throughput and overlay improvements for high volume semiconductor manufacturing using nanoimprint lithography
Author(s): Osamu Morimoto; Takehiko Iwanaga; Yukio Takabayashi; Keita Sakai; Wei Zhang; Anshuman Cherala; Se-Hyuk Im; Mario Meissl; Jin Choi
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Paper Abstract

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, we review progress on pattern capability, throughput, mask life and overlay. To minimize distortion and improve overlay, a Drop Pattern Compensation (DPC) method has been implemented to minimize the added overlay distortion terms. In this paper we describe the origins of the out of plane errors, and describe the method used to correct these errors along with some examples. Improvements to both cross matched machine overlay (XMMO) and imprint mix and match overlay (IMMO) are presented.

Paper Details

Date Published: 26 September 2019
PDF: 10 pages
Proc. SPIE 11148, Photomask Technology 2019, 111480M (26 September 2019); doi: 10.1117/12.2535912
Show Author Affiliations
Osamu Morimoto, Canon Inc. (Japan)
Takehiko Iwanaga, Canon Inc. (Japan)
Yukio Takabayashi, Canon Inc. (Japan)
Keita Sakai, Canon Inc. (Japan)
Wei Zhang, Canon Nanotechnologies, Inc. (United States)
Anshuman Cherala, Canon Nanotechnologies Inc. (United States)
Se-Hyuk Im, Canon Nanotechnologies Inc. (United States)
Mario Meissl, Canon Nanotechnologies Inc. (United States)
Jin Choi, Canon Nanotechnologies Inc. (United States)


Published in SPIE Proceedings Vol. 11148:
Photomask Technology 2019
Jed H. Rankin; Moshe E. Preil, Editor(s)

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