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Proceedings Paper

Detection and mitigation of furnace anneal induced distortions at the wafer edge
Author(s): Leon van Dijk; Anne-Laure Charley; Maarten Stokhof; Ronald Otten; Sven Van Elshocht; Bert Jongbloed; Philippe Leray; Richard van Haren
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Paper Abstract

Every advance in technology node challenges the semiconductor industry to achieve even tighter on-product overlay (OPO) requirements. With the latest immersion scanners performing well below the sub-2-nm overlay level, the OPO budget is more and more determined by non-lithography contributors. Achieving the tight overlay specifications in a high-volume manufacturing environment is therefore far from trivial, especially in the wafer edge region where processing is even less well controlled. For example, Reactive Ion Etch (RIE), the deposition of stressed thin films and the presence of significant intra-field (or intra-die) stress distributions are all known to cause localized distortions in the wafer edge region. Annealing steps during integrated circuit manufacturing are another source of wafer deformation. Furnace anneal is one particular type of annealing step. During furnace anneal processing, many wafers are heated-up simultaneously and wafers stay at elevated temperatures for a fixed time on the order of minutes to hours. Although in general, furnace anneal does not cause significant wafer deformations, local distortions are sometimes observed in the wafer edge region by using standard boats at higher anneal temperatures. In this work, we have setup a controlled experiment to characterize the local distortions that can be induced by furnace anneal processes. To this end, wafers are processed with various furnace anneal settings, i.e. temperature and ramp rate, and two different boat types are used. The induced distortions are accurately and densely measured on an NXT:1970Ci scanner using its SMASH alignment system. We will see that, depending on the process conditions and boat type, local distortions occur at the wafer edge. The locations of these distortions coincide with the wafer support positions of the boat and therefore they are also referred to as boat marks. Several solution directions for mitigating furnace anneal induced distortions will be discussed. A very effective solution is the employment of an optimized boat design that, depending on the process conditions, can prevent the localized distortions at elevated temperatures. It would therefore be beneficial to have a detection system in place that can detect and consequently trigger actions to mitigate furnace anneal induced distortions during the development phase of anneal processing steps. We will demonstrate that the scanner can be used as such a detection system as its inline metrology is able to detect signatures related to the boat marks.

Paper Details

Date Published: 29 August 2019
PDF: 8 pages
Proc. SPIE 11177, 35th European Mask and Lithography Conference (EMLC 2019), 1117714 (29 August 2019); doi: 10.1117/12.2535636
Show Author Affiliations
Leon van Dijk, ASML Netherlands B.V. (Netherlands)
Anne-Laure Charley, IMEC (Belgium)
Maarten Stokhof, ASM Belgium N.V. (Belgium)
Ronald Otten, ASML Netherlands B.V. (Netherlands)
Sven Van Elshocht, IMEC (Belgium)
Bert Jongbloed, ASM Belgium N.V. (Belgium)
Philippe Leray, IMEC (Belgium)
Richard van Haren, ASML Netherlands B.V. (Netherlands)


Published in SPIE Proceedings Vol. 11177:
35th European Mask and Lithography Conference (EMLC 2019)
Uwe F.W. Behringer; Jo Finders, Editor(s)

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