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Proceedings Paper

Study of mask and wafer co-design that utilizes a new extreme SIMD approach to computing in memory manufacturing: full-chip curvilinear ILT in a day
Author(s): Linyong Pang; Ezequiel Vidal Russell; Bill Baggenstoss; Michael Lee; Jennefir Digaum; Ming-Chuan Yang; P. Jeffrey Ungar; Ali Bouaricha; Kechang Wang; Bo Su; Ryan Pearman; Aki Fujimura
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Paper Abstract

In advanced semiconductor memory manufacturing, mask and lithography are critical for patterning. In this paper we jointly study the benefits of a mask and wafer co-design that utilizes a new extreme single instruction multiple data (SIMD) approach to computing. Wafer results will be shown demonstrating the benefits of the approach. Unlike traditional EDA software that runs on customers’ computer farm, this new approach leverages and maximizes GPU acceleration. In this study, software speed and quality, mask writing strategy, wafer pattern fidelity and process window are examined and analyzed. Inverse lithography technology (ILT) has been seen as a promising solution to many of the challenges of advanced-node lithography, whether optical or EUV. However, the runtimes associated with this computational technique have limited its practical application. Until now, it has been used for critical “hotspots” on chips, but has not been used for entire chips. The solution to the runtime problem for ILT has been particularly vexing, as the traditional approach to runtime improvement – partitioning and stitching – has failed to produce satisfactory results, either in terms of runtime or in terms of quality. D2S has adopted an entirely new, stitchless approach, creating a holistically conceived, purpose-built system for ILT, This system includes a unique GPU-accelerated approach that emulates a single, giant GPU/CPU pair that can compute an entire full-chip ILT solution at once. This novel approach, systematically designed for ILT and GPU acceleration, makes full-chip ILT a practical reality in production for the first time. For the most advanced DRAM manufacturing using 193nm immersion lithography, every aspect of design, mask, and lithography, including quality of the process, accuracy, and turn-around-time, need to be optimized. Any new technique that significantly improve one or more elements of such complete process are welcome. Recently a number of new technologies, such as multi-beam mask writer, GPU accelerated computing for mask and wafer, are emerged and are reshaping the mask and lithography. This new stitchless full chip curvilinear ILT is applied to memory chip making. We will show mask making and wafer print results, including pattern fidelity and process window, to show the actual benefits of such technologies for semiconductor manufacturing.

Paper Details

Date Published: 3 October 2019
PDF: 16 pages
Proc. SPIE 11148, Photomask Technology 2019, 111480U (3 October 2019); doi: 10.1117/12.2534629
Show Author Affiliations
Linyong Pang, D2S, Inc. (United States)
Ezequiel Vidal Russell, Micron Technology, Inc. (United States)
Bill Baggenstoss, Micron Technology, Inc. (United States)
Michael Lee, Micron Technology, Inc. (United States)
Jennefir Digaum, Micron Technology, Inc. (United States)
Ming-Chuan Yang, Micron Technology, Inc. (United States)
P. Jeffrey Ungar, D2S, Inc. (United States)
Ali Bouaricha, D2S, Inc. (United States)
Kechang Wang, D2S, Inc. (United States)
Bo Su, D2S, Inc. (United States)
Ryan Pearman, D2S, Inc. (United States)
Aki Fujimura, D2S, Inc. (United States)

Published in SPIE Proceedings Vol. 11148:
Photomask Technology 2019
Jed H. Rankin; Moshe E. Preil, Editor(s)

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