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Proceedings Paper

High-speed photonic CMOS technology for logic and memory applications
Author(s): James N. Pan
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Paper Abstract

This paper reports a novel optoelectronic sub-7nm CMOS transistor, which can be fabricated with a multiple quantum well (MQW) laser or tunnel light emitting diode (TLED) in the drain region, and an underlying avalanche breakdown photo diode (APD). The CMOS, photonic device, and APD are integrated as one transistor. The methods described in this report are fully compatible with a conventional CMOS process flow, including the FINFET technology, and scalable for future sub-10nm technology nodes. The Ion/Ioff ratio may surpass 10nm CMOS with these additional optoelectronic components.

Paper Details

Date Published: 3 September 2019
PDF: 11 pages
Proc. SPIE 11089, Nanoengineering: Fabrication, Properties, Optics, Thin Films, and Devices XVI, 110891I (3 September 2019); doi: 10.1117/12.2524557
Show Author Affiliations
James N. Pan, American Enterprise and License Co. (United States)

Published in SPIE Proceedings Vol. 11089:
Nanoengineering: Fabrication, Properties, Optics, Thin Films, and Devices XVI
Balaji Panchapakesan; André-Jean Attias, Editor(s)

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