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Proceedings Paper

Design and simulation of image nonlinear processing relational preprocessor based on iterational sorting node
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Paper Abstract

In this paper, we propose a new iterative process of sorting an array of signals, which differs from the known structures of sorting signals by uniformity, versatility, which allows direct and inverse sorting of an array of analog or digital signals. The basic elements of the proposed sorting structures are simple relational nodes for analogue signals from sensor devices and cameras. Such elements can be implemented on a different element basis, including, on devices for selecting a maximum or minimum of two analog or digital signals, which are implemented, in one of the variants, on CMOS current mirrors and carry out the function of continuous logic limited difference. We offer optoelectronic implementation of such basic relational element and a homogeneous sorting structure on such elements, consisting of two layers and a multichannel sampling and holding device. Nine signals corresponding to a selection window of a matrix sensor are fed to this structure, we sort them in five iterative steps, and at the output we receive the signals sorted by the rank, which, using the code controlled programmable multiplexer, generates an output signal, corresponding to the selected rank. We evaluate the technical parameters of such a relational preprocessor for nonlinear signal processing in image processors, sorting networks, multichannel parallel type sensor, processing, and encoding systems. The base cells consist of no more than 20 CMOS 1.5μm transistors, the total power consumption of the sorting node on 10 continuously logical base cells (CL BC) is 2mW, the supply voltage is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the conversion cycle is 10μs, but can be improved by selecting other transistors and some modifications of the circuits. Such mixed analog processor is modeled in PSpice OrCad. The paper considers results of design and modeling of CL BC based on photosensitive cells with an extended electronic circuit and current mirrors (CM) with functions of preliminary subsequent analogue processing for creating picture type image processors (IP) with matrix parallel inputs-outputs. Such BCs and sorting nodes based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level. We consider CL BC for methods of selection and rank preprocessing. In contrast to our previous works here we will dwell more on analogue preprocessing schemes for signals of neighboring cells. Let us show how the introduction of iterative sorting nodes extends the range of functions performed by the IPs. Examples of image processing with proposed preprocessor are simulated in MathCad and show the field of application of such coprocessors and new prospects for realization of linear and matrix photo-electronic structures with matrix operands. The essential difference is that the structure is iterative and allows to significantly reducing hardware costs in comparison with other hardware implementations of sorting networks. We discuss some aspects of possible rules and principles of learning and programmable configuration for the required function, relational work, and the implementation of hardware blocks for modifying such processors.

Paper Details

Date Published: 11 April 2019
PDF: 15 pages
Proc. SPIE 11028, Optical Sensors 2019, 110282X (11 April 2019); doi: 10.1117/12.2524114
Show Author Affiliations
Vladimir G. Krasilenko, Vinnitsa Social Economy Institute (Ukraine)
Alexander A. Lazarev, Vinnytsia National Technical Univ. (Ukraine)
Diana V. Nikitovich, Vinnytsia National Technical Univ. (Ukraine)


Published in SPIE Proceedings Vol. 11028:
Optical Sensors 2019
Francesco Baldini; Jiri Homola; Robert A. Lieberman, Editor(s)

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