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Proceedings Paper

Fabrication and properties of SOI-based planar silicon nanowire arrays
Author(s): Alexander E. Rogozhin; Andrey V. Miakonkikh; Andrey A. Tatarintsev; Konstantin V. Rudenko
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Paper Abstract

The fabrication of silicon nanostructures for microelectronic applications is of great interest. We employed two-stage technology of precise anizotropic plasma etching of silicon over e-beam resist and isotropic removal of thermally oxidised defected surface layer of silicon by wet etch to fabricate planar silicon nanowire arrays. Silicon nanowires with diameter of 10-30 nm were obtained. It is simple to get nanowires without oxide or covered with thermal SiO2. Conductivity of obtained silicon nanowire arrays before and after oxidation was measured. It was found that after oxidation and removal of oxide layer conductivity increases dramatically.

Paper Details

Date Published: 15 March 2019
PDF: 6 pages
Proc. SPIE 11022, International Conference on Micro- and Nano-Electronics 2018, 1102222 (15 March 2019); doi: 10.1117/12.2522457
Show Author Affiliations
Alexander E. Rogozhin, Institute of Physics and Technology of RAS (Russian Federation)
Moscow Institute of Physics and Technology (Russian Federation)
Andrey V. Miakonkikh, Institute of Physics and Technology of RAS (Russian Federation)
Moscow Institute of Physics and Technology (Russian Federation)
Andrey A. Tatarintsev, Institute of Physics and Technology of RAS (Russian Federation)
Konstantin V. Rudenko, Institute of Physics and Technology of RAS (Russian Federation)


Published in SPIE Proceedings Vol. 11022:
International Conference on Micro- and Nano-Electronics 2018
Vladimir F. Lukichev; Konstantin V. Rudenko, Editor(s)

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