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Proceedings Paper

Design of neuron-calculators for the normalized equivalence of two matrix arrays based on FPGA for self-learning equivalently convolutional neural networks (SLE_CNNs)
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Paper Abstract

First, in the introduction, we will show the urgent need to create neuron-calculators (NCs) for the normalized equivalence of two matrix arrays for self-learning equivalently-convolutional neural networks (SLE_CNNs), video processors for parallel image processing with enhanced functionality. Consider promising areas of application of such single and multichannel neuron-calculators as high-precision, high-speed and high-performance accelerators for hardware systems and architectures for recognition, classification, image categorization, in particular for 2D-image space-invariant associative memory structures, SLE_CNNs based on the equivalence paradigm. Next, we will consider and analyze the theoretical foundations, the mathematical apparatus of matrix and continuous logic, and their basic operations, show their functional completeness, evaluate their advantages and prospects for application in the design of biologically inspired devices and systems for processing and analyzing signal arrays. We will show that some functions of continuous logic, including operations of normalized equivalence of vector and matrix signals, operation of the bounded difference of continuous logic, are the powerful basis for designing advanced accelerator calculators, microcells for hybrid (mixed) analog-to-digital transformations, comparisons and calculations of characteristics. Next, we will consider in more detail the design and simulation aspects of such digital neuron-calculators for the normalized equivalence of two matrix arrays based on FPGA, including their various modifications, depending on the dimension and the number of compared arrays. We will propose our approach for calculation of the normalized equivalence functions comparing current fragments of images and filters with dimensions 3×3, 7×7, 15×15, and others. The project is executed on FPGA ALTERA MAXII. The simulation was done with Intel Quartus Prime 17 and showed that in a single chip it is possible to place four parallel working neuron calculators processing 4 filters with a size of 15×15. The approximate processing time is less than 5μs. Power consumption is 50mW for supply voltage of 2.5V and clock frequency equals to 50MHz. We will also consider modifications that improve performance for different filter size. We show the results of modeling the proposed new implementations of NCs, we estimates and compare them.

Paper Details

Date Published: 14 May 2019
PDF: 12 pages
Proc. SPIE 10996, Real-Time Image Processing and Deep Learning 2019, 109960P (14 May 2019); doi: 10.1117/12.2518206
Show Author Affiliations
Vladimir G. Krasilenko, Vinnitsa Social Economy Institute (Ukraine)
Alexander A. Lazarev, Vinnitsa State Technical Univ. (Ukraine)
Diana V. Nikitovich, Vinnitsa State Technical Univ. (Ukraine)

Published in SPIE Proceedings Vol. 10996:
Real-Time Image Processing and Deep Learning 2019
Nasser Kehtarnavaz; Matthias F. Carlsohn, Editor(s)

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