Share Email Print

Proceedings Paper

Process window-based feature and die failure rate prediction
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Critical edge placement margins continue to shrink in advanced designs, Over the years, various methods have been used to quantify the lithographic “process window”, often in terms of allowable CD variation. Ultimately however, what is of most interest is the margin for chip failure, either due to hard pinching, bridging, or pattern collapse of a single layer, or interlayer critical edge placement errors. The latter could include insufficient overlap between layers such as metal and via, or unwanted bridging of patterns between layers. We present here a framework for estimating the failure rate for any individual feature given an assumed manufacturing distribution of primary patterning variables such as dose, focus, mask dimension, and perhaps overlay. If the failure rate for all features within the die is known, then by extension the failure rate for the entire die can be known. Since estimating the process window exhaustively for all in-die locations is not possible, we first identify process window limiting features, then utilize this knowledge to estimate overall die failure rates. This method can account for both systematic failure of an individual feature instance as well as stochastic failure for repeating patterns.

Paper Details

Date Published: 20 March 2019
PDF: 10 pages
Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 109620B (20 March 2019); doi: 10.1117/12.2516101
Show Author Affiliations
John Sturtevant, Mentor Graphics Corp. (United States)
Lianghong Yin, Mentor Graphics Corp. (United States)
Young Chang Kim, Mentor Graphics Corp. (United States)
Shumay Shang, Mentor Graphics Corp. (United States)
Andrew Burbine, Mentor Graphics Corp. (United States)
Chris Clifford, Mentor Graphics Corp. (United States)
Kostas Adam, Mentor Graphics Corp. (United States)

Published in SPIE Proceedings Vol. 10962:
Design-Process-Technology Co-optimization for Manufacturability XIII
Jason P. Cain, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?