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Proceedings Paper

Impact of sequential infiltration synthesis (SIS) on roughness and stochastic nano-failures for EUVL patterning
Author(s): Pieter Vanelderen; Victor Blanco; Ming Mao; Yoann Tomczak; David de Roest; Nicola Kissoon; Paulina Rincon Delgadillo; Gijsbert Rispens; Guido Schiffelers; Abhinav Pathak; Frederic Lazzarino; Danilo De Simone; Etienne de Poortere; Moyra Mc Manus; Daniele Piumi; Eric Hendrickx; Geert Vandenberghe
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Paper Abstract

Enhanced EUV lithography (EUVL) resist performance, combined with optimized post processing techniques, are vital to ensure continued scaling and meet the requirements for the industry N5 node and beyond. Sequential infiltration synthesis (SIS) is a post lithography technique that has the potential to significantly improve the EUVL patterning process for stochastic nano-failures and line roughness, both major topics in EUV lithography research. SIS is an ALD-like technique that infiltrates polymeric photoresists, forming a metal framework using the lithography pattern as a template. Hardening of the photoresist improves the pattern quality and gives more flexibility to subsequent pattern transfer steps. We have evaluated the performance of SIS for an EUV Chemically Amplified Resist (CAR) platform printing 32 nm pitch line/space patterns and ultimately structures that are representative of standard semiconductor manufacturing. A combined lithography-SIS-etch process and a standard lithography-etch process were optimized for an industry relevant stack with pattern transfer into a TiN layer. This allows for the first time a justified comparison between a EUVL-SIS and a standard EUVL patterning process, showing the benefits of SIS regarding roughness, exposure latitude and nano-failure mitigation. Power Spectral Density (PSD) analysis accurately demonstrates and explains the type of roughness improvement. Nano-failure analysis is done by measuring large areas at different exposure doses and shows the improvement of the nano-failure free window when applying a EUVL-SIS patterning process. We conclude by examining to which extent combining the best lithography process with an optimized SIS step will lead to a better roughness and nano-failure performance, essential to meeting industry requirements.

Paper Details

Date Published: 26 March 2019
PDF: 15 pages
Proc. SPIE 10957, Extreme Ultraviolet (EUV) Lithography X, 109570S (26 March 2019); doi: 10.1117/12.2515503
Show Author Affiliations
Pieter Vanelderen, IMEC (Belgium)
Victor Blanco, IMEC (Belgium)
Ming Mao, IMEC (Belgium)
Yoann Tomczak, ASM (Belgium)
David de Roest, ASM (Belgium)
Nicola Kissoon, ASML (Netherlands)
Paulina Rincon Delgadillo, IMEC (Belgium)
Gijsbert Rispens, ASML (Netherlands)
Guido Schiffelers, ASML (Netherlands)
Abhinav Pathak, IMEC (Belgium)
Frederic Lazzarino, IMEC (Belgium)
Danilo De Simone, IMEC (Belgium)
Etienne de Poortere, ASML (Netherlands)
Moyra Mc Manus, ASML (Netherlands)
Daniele Piumi, ASM (Belgium)
Eric Hendrickx, IMEC (Belgium)
Geert Vandenberghe, IMEC (Belgium)


Published in SPIE Proceedings Vol. 10957:
Extreme Ultraviolet (EUV) Lithography X
Kenneth A. Goldberg, Editor(s)

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