Share Email Print

Proceedings Paper

Accuracy improvement of electrical characteristics estimation for sub-20nm FDSOI devices with non-rectangular gates
Author(s): Jia-Syun Cai; Sheng-Wei Chien; Xin-Yang Zheng; Chien-Lin Lee; Kuen-Yu Tsai
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

In subwavelength lithography, the printed patterns on the silicon wafer suffer from geometric distortions and different from the original design. These non-rectangular patterns can affect electrical characteristics and circuit performances seriously. In this work, we extend the verification of location-dependent weighting method and further propose three single conventional equivalent gate length (EGL) extraction methods for representing each non-rectangular gate transistor with a single EGL model. These methods are applied to sub-20nm FDSOI circuits to predict the postlithography performances. An in-house Extreme Ultraviolet Lithography (EUVL) simulation tool is utilized for nonrectangular pattern simulation. Shape information is imported to TCAD to construct 3D non-rectangular FDSOI transistor models. The accuracy of the location-dependent weighting method and EGL extraction methods are verified with TCAD circuit simulations. A 2D EGL circuit simulation method in TCAD is proposed instead of 3D EGL method to reduce the simulation time required. Preliminary simulation results indicate that weighting factors can improve the accuracy of electrical characteristics estimation, especially in leakage current analysis. On average, the off-state EGL (EGLoff) with weightings is good enough. These methods could be used to simulate the non-rectangular transistors applied to sub-20nm FDSOI circuits including 6T-SRAM caused by non-ideal optical effects in industrial processes.

Paper Details

Date Published: 20 March 2019
PDF: 22 pages
Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 109620I (20 March 2019); doi: 10.1117/12.2515186
Show Author Affiliations
Jia-Syun Cai, National Taiwan Univ. (Taiwan)
Sheng-Wei Chien, National Taiwan Univ. (Taiwan)
Xin-Yang Zheng, National Taiwan Univ. (Taiwan)
Chien-Lin Lee, National Taiwan Univ. (Taiwan)
Kuen-Yu Tsai, National Taiwan Univ. (Taiwan)

Published in SPIE Proceedings Vol. 10962:
Design-Process-Technology Co-optimization for Manufacturability XIII
Jason P. Cain, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?