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Proceedings Paper

Smart implant-layer overlay metrology to enable fab cycle time reduction
Author(s): Leon van Dijk; Faegheh Hasibi; Maialen Larrañaga; Anne Pastol; Auguste Lam; Richard van Haren
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Paper Abstract

Overlay is one of the most critical design parameters in integrated circuit manufacturing. Maintaining good overlay performance during manufacturing is therefore essential in order to obtain high yield and to ensure that the performance and reliability of the eventual semiconductor device is according to specifications. For that reason, optical metrology is nowadays extensively used in any production facility for overlay monitoring and process control. Overlay metrology is typically required after each lithography step for (nearly) every lot. The number of process and lithograpy steps have increased significantly with advancing technology nodes and consequently there is an increased demand for overlay metrology. Although the benefits of overlay metrology are obvious, the use of metrology should be kept at acceptable levels as it adds cost and increases fab cycle time. Virtual overlay metrology, the replacement of some real overlay measurements with predicted values, is an effective solution for keeping the need for overlay metrology under control.

Paper Details

Date Published: 26 March 2019
PDF: 13 pages
Proc. SPIE 10959, Metrology, Inspection, and Process Control for Microlithography XXXIII, 109591H (26 March 2019); doi: 10.1117/12.2515185
Show Author Affiliations
Leon van Dijk, ASML Netherlands B.V. (Netherlands)
Faegheh Hasibi, ASML Netherlands B.V. (Netherlands)
Maialen Larrañaga, ASML Netherlands B.V. (Netherlands)
Anne Pastol, ASML Netherlands B.V. (Netherlands)
Auguste Lam, STMicroelectronics S.A. (France)
Richard van Haren, ASML Netherlands B.V. (Netherlands)

Published in SPIE Proceedings Vol. 10959:
Metrology, Inspection, and Process Control for Microlithography XXXIII
Vladimir A. Ukraintsev; Ofer Adan, Editor(s)

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