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Proceedings Paper

FEOL CMP modeling challenges and solution in 3D NAND
Author(s): Yang Li; Rick Li; Peng Jiang; Luming Fan; Aman Zheng; Sicong Wang; Guangyi Wang; Chunshan Du; Zhengfang Liu; Ruben Ghulghazaryan; Qijian Wan; Xinyi Hu
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Paper Abstract

Chemical-mechanical polishing (CMP) is a key process that reduces chip topography variation during manufacturing. Any variation outside of specifications can cause hotspots, which negatively impact yield. As technology moves forward, especially in memory processes like 3D NAND, high-quality surface planarity is required to overcome manufacturing challenges in each process step. Any topography variation in the front-end-of-line (FEOL) must be taken into consideration, as it may dramatically impact the surface planarity achieved by subsequent manufacturing steps. Rule-based checking of the design is not sufficient to discover all potential CMP hotspots. An accurate FEOL CMP model is necessary to predict design-induced CMP hotspots and optimize the use of dummy fill to alleviate manufacturing challenges. While back-end-of-line (BEOL) CMP modeling technology has matured in recent years, FEOL CMP modeling is still facing multiple challenges. This paper describes how an accurate FEOL CMP model may be built, and how interlayer dielectric (ILD) layer CMP simulations may be used for 3D NAND design improvement. In the example of ILD CMP model validation for a 3D NAND product, it is shown that the model predictions match well with the silicon data and that the model may successfully be used for hotspot prediction in production designs prior to manufacturing.

Paper Details

Date Published: 20 March 2019
PDF: 6 pages
Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096211 (20 March 2019); doi: 10.1117/12.2515167
Show Author Affiliations
Yang Li, Yangtze Memory Technologies Co., Ltd. (China)
Rick Li, Yangtze Memory Technologies Co., Ltd. (China)
Peng Jiang, Yangtze Memory Technologies Co., Ltd. (China)
Luming Fan, Yangtze Memory Technologies Co., Ltd. (China)
Aman Zheng, Yangtze Memory Technologies Co., Ltd. (China)
Sicong Wang, Yangtze Memory Technologies Co., Ltd. (China)
Guangyi Wang, Yangtze Memory Technologies Co., Ltd. (China)
Chunshan Du, Yangtze Memory Technologies Co., Ltd. (China)
Zhengfang Liu, Mentor Graphics Shanghai Electronic Technology Co. (China)
Ruben Ghulghazaryan, Mentor Graphics Corp. (Armenia)
Qijian Wan, Mentor Graphics Shanghai Electronic Technology Co. (China)
Xinyi Hu, Mentor Graphics Shanghai Electronic Technology Co. (China)


Published in SPIE Proceedings Vol. 10962:
Design-Process-Technology Co-optimization for Manufacturability XIII
Jason P. Cain, Editor(s)

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