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Proceedings Paper

Optimization of read and write performance of SRAMs for node 5nm and beyond
Author(s): Khaja Ahmad Shaik; Mohit Gupta; Pieter Weckx; Alessio Spessot
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Paper Abstract

Scaled technology node, SRAMs suffer from increased Bit Line (BL) and Word Line (WL) resistance. To solve these issues, we present SRAM bit-level BL and WL metallization and options suitable for both SADP an EUV. We also present Buried power Rail (BPR) SRAM as enablers for high density SRAM cells (HD-111) in scaled technology nodes for 5nm and beyond and illustrate system level advantages of BPR SRAM with BPR based power delivery network of a hard macro like Arm 64-bit CPU.

Paper Details

Date Published: 20 March 2019
PDF: 9 pages
Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096203 (20 March 2019); doi: 10.1117/12.2515162
Show Author Affiliations
Khaja Ahmad Shaik, IMEC (Belgium)
Mohit Gupta, IMEC (Belgium)
Pieter Weckx, IMEC (Belgium)
Alessio Spessot, IMEC (Belgium)


Published in SPIE Proceedings Vol. 10962:
Design-Process-Technology Co-optimization for Manufacturability XIII
Jason P. Cain, Editor(s)

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