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Proceedings Paper

Copper interconnect topography simulation in 3D NAND designs
Author(s): Yang Li; Rick Li; Peng Jiang; Luming Fan; Aman Zheng; Sicong Wang; Guangyi Wang; Zhengfang Liu; Chunshan Du; Ruben Ghulghazaryan; Qijian Wan; Xinyi Hu
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Paper Abstract

Vertical NAND (3D NAND) designs provide unprecedented improvements in input/output (I/O) performance and storage density, but require additional analysis to ensure manufacturing and market success. While 3D stacked architectures greatly reduce chip area at advanced technology nodes, greater topology uniformity is essential, not only for inter-layers stacking, but also for the chip bonding process. As the link between design and manufacturing, design for manufacturing (DFM) predicts potential manufacturing issues during the design stage, enabling design teams to modify the layout and mitigate the risk. The copper interconnect process can be modeled through multiple process steps, from film stacking, etch, and copper deposition to polishing. The simulated topology of a given design predicts potential risky areas that may be fixed by changing designs or inserting dummy fill prior to manufacturing. This simulation is a useful technique during yield ramp-up, and can shorten the cycle from design to manufacturing. This paper presents a solution for BEOL CMP modeling and analysis on BEOL copper interconnect of a 3D NAND flow.

Paper Details

Date Published: 20 March 2019
PDF: 6 pages
Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096210 (20 March 2019); doi: 10.1117/12.2515161
Show Author Affiliations
Yang Li, Yangtze Memory Technologies Co., Ltd. (China)
Rick Li, Yangtze Memory Technologies Co., Ltd. (China)
Peng Jiang, Yangtze Memory Technologies Co., Ltd. (China)
Luming Fan, Yangtze Memory Technologies Co., Ltd. (China)
Aman Zheng, Yangtze Memory Technologies Co., Ltd. (China)
Sicong Wang, Yangtze Memory Technologies Co.,Ltd. (China)
Guangyi Wang, Yangtze Memory Technologies Co., Ltd. (China)
Zhengfang Liu, Mentor Graphics Shanghai Electronic Technology Co. (China)
Chunshan Du, Mentor Graphics Shanghai Electronic Technology Co. (China)
Ruben Ghulghazaryan, Mentor Graphics Corp. (Armenia)
Qijian Wan, Mentor Graphics Corp. (China)
Xinyi Hu, Mentor Graphics Corp. (China)


Published in SPIE Proceedings Vol. 10962:
Design-Process-Technology Co-optimization for Manufacturability XIII
Jason P. Cain, Editor(s)

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