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Proceedings Paper

Tilted ion implantation of spin-coated SiARC films for sub-lithographic and two-dimensional patterning
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Paper Abstract

Tilted ion implantation (TII) used in conjunction with pre-existing masking features on the surface of a wafer is a promising cost-effective method for self-aligned double-patterning. Recent work experimentally demonstrated pitch-halving by masked TII into a thermally grown SiO2 hard-mask layer: the wet etch rate of SiO2 increases dramatically if the implant-induced damage exceeds a threshold level, so that implanted regions (vs. non- implanted SiO2 regions) can be selectively removed in dilute hydrofluoric acid solution. In this work, this method is extended to a silicon anti-reflection coating (SiARC) deposited by spin-coating and processed at temperatures compatible with back-end-of-line processing. Negative-tone patterning is achieved by implanting a 10 nm-thick SiARC film with Ar+ species at low energies (less than 5 keV) to reduce the wet etch rate. In general, the higher the implant dose, the greater the etch rate contrast between implanted vs. non-implanted regions of the SiARC layer. In principle, the TII method can be extended to form patterns with dimensions that extend in two orthogonal directions, i.e., two-dimensional (2D) patterns. In this work, the use of TII for 2D patterning is investigated via Monte Carlo simulations to study the effect of implantation dose and varying degrees of overlap between implanted regions extending along orthogonal directions. Stochastic effects on pattern fidelity are systematically investigated. The capability of TII to form sub-lithographic 2D patterns makes it advantageous for extending the era of Moores Law.

Paper Details

Date Published: 26 March 2019
PDF: 8 pages
Proc. SPIE 10958, Novel Patterning Technologies for Semiconductors, MEMS/NEMS, and MOEMS 2019, 109581F (26 March 2019); doi: 10.1117/12.2515154
Show Author Affiliations
Thomas R. Rembert, Univ. of California, Berkeley (United States)
Daniel Connelly, Univ. of California, Berkeley (United States)
Shalini Sharma, JSR Micro, Inc. (United States)
Leonard Rubin, Axcelis Technologies, Inc. (United States)
Tsu-Jae King Liu, Univ. of California, Berkeley (United States)

Published in SPIE Proceedings Vol. 10958:
Novel Patterning Technologies for Semiconductors, MEMS/NEMS, and MOEMS 2019
Martha I. Sanchez; Eric M. Panning, Editor(s)

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