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Proceedings Paper

Patterning challenges for beyond 3nm logic devices: example of an interconnected magnetic tunnel junction
Author(s): N. A. Thiam; D. Wan; L. Souriau; K. Babaei Gavan; N. Rassoul; J. Swerts; S. Couet; E. Raymenants; J. Jussot; D. Trivkovic; M. Ercken; C. J. Wilson; I. P. Radu
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Paper Abstract

In this paper, patterning challenges that led to the fabrication of a first Spin Torque Majority Gate (STMG) device are explored. We have highlighted key process module developments from the Magnetic Tunnel Junctions (MTJs) pillar patterning to dual damascene scheme wiring module. Spin devices such as STMG have already been proposed as a replacement for conventional CMOS transistors. The main challenge to their experimental demonstration remains the successful fabrication of connected MTJs through a ferromagnetic layer, allowing spin transport across the gate. We propose a new etching approach utilizing Ion Beam Etching (IBE), to be able to pattern the MTJs with high precision and with less damage to the magnetic layers. Furthermore, we have introduced Electron-beam lithography to further scale down the device geometries. This development paves the way towards a fully integrated STMG device for Spin Logic applications.

Paper Details

Date Published: 26 March 2019
PDF: 14 pages
Proc. SPIE 10958, Novel Patterning Technologies for Semiconductors, MEMS/NEMS, and MOEMS 2019, 109580Y (26 March 2019); doi: 10.1117/12.2515086
Show Author Affiliations
N. A. Thiam, Imec (Belgium)
D. Wan, Imec (Belgium)
L. Souriau, Imec (Belgium)
K. Babaei Gavan, Imec (Belgium)
N. Rassoul, Imec (Belgium)
J. Swerts, Imec (Belgium)
S. Couet, Imec (Belgium)
E. Raymenants, Imec (Belgium)
J. Jussot, Imec (Belgium)
D. Trivkovic, Imec (Belgium)
M. Ercken, Imec (Belgium)
C. J. Wilson, Imec (Belgium)
I. P. Radu, Imec (Belgium)

Published in SPIE Proceedings Vol. 10958:
Novel Patterning Technologies for Semiconductors, MEMS/NEMS, and MOEMS 2019
Martha I. Sanchez; Eric M. Panning, Editor(s)

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