In 5 nm FinFET technology and beyond, SRAM cell size reduction to 6 tracks is required with a fin pitch of 24 nm. Fin depopulation is mandatory to enable the area scaling, but it becomes challenging at small pitches. In the first part, each process flow is simulated in order to obtain a 3D model of a FinFET SRAM device. Layout dependent effects on silicon and process non-idealities are characterized in a second part and used to calibrate the 3D model. In the third part, a process sensitivity analysis is conducted to compare the impact of overlay and CD variations on various options.

Date Published: 25 March 2019
PDF: 7 pages
Proc. SPIE 10960, Advances in Patterning Materials and Processes XXXVI, 109600N (25 March 2019); doi: 10.1117/12.2514927

Published in SPIE Proceedings Vol. 10960:
Advances in Patterning Materials and Processes XXXVI
Roel Gronheid; Daniel P. Sanders, Editor(s)