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Proceedings Paper

Development of standard samples with programmed defects for evaluation of pattern inspection tools
Author(s): Susumu Iida; Takamitsu Nagai; Takayuki Uchiyama
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Paper Abstract

Standard wafers with programmed defects (PDs) were fabricated to evaluate charge control techniques, resolution, and defect detection capabilities of pattern inspection tools for 7-nm and smaller nodes. To evaluate charge control techniques, the PDs were formed in line and space (LS) patterns. PDs were also formed below contact holes as programmed etching residues. These PDs were detected by a voltage contrast inspection technique. Image distortion by charging was also evaluated with the use of a wafer in a multibeam secondary electron microscope (SEM) and projection type inspection systems. Patterns with PDs were also formed on different subsurface structures. The effects of subsurface structures on the defect detection capability were evaluated based on this wafer. Another type of wafer having small defects approximately 5 nm in size on 16- to 12-nm half pitch (hp) LS patterns on a 12-inch Si-wafer, was fabricated by electron beam lithography. This wafer allowed evaluation of the defect detection capability of PDs having different shapes and sizes, such as protrusion, intrusion, bridge and open defects, on dense patterns for 7-nm and smaller nodes. Moreover, extremely small protrusion defects, with a size of 1 nm, and small bridge defects (as narrow as 1 nm) were also fabricated into LS patterns with ultra-low line-edge-roughness on a Si (110) substrate. This patterned substrate was mounted into a 12-inch Si wafer, and we evaluated the performance of tools for 12-inch wafer fabrication. We proposed a method to verify the true LER/LWR by CD-SEM measurements.

Paper Details

Date Published: 26 March 2019
PDF: 13 pages
Proc. SPIE 10959, Metrology, Inspection, and Process Control for Microlithography XXXIII, 109590J (26 March 2019); doi: 10.1117/12.2514897
Show Author Affiliations
Susumu Iida, Evolving Nano-process Infrastructure Development Ctr., Inc. (Japan)
Takamitsu Nagai, Evolving Nano-process Infrastructure Development Ctr., Inc. (Japan)
Takayuki Uchiyama, Evolving Nano-process Infrastructure Development Ctr., Inc. (Japan)

Published in SPIE Proceedings Vol. 10959:
Metrology, Inspection, and Process Control for Microlithography XXXIII
Vladimir A. Ukraintsev; Ofer Adan, Editor(s)

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