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Proceedings Paper

CFET standard-cell design down to 3Track height for node 3nm and below
Author(s): S. M. Y. Sherazi; J. K. Chae; P. Debacker; L. Matti; D. Verkest; A. Mocuta; R. H. Kim; A. Spessot; A. Dounde; J. Ryckaert
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Paper Abstract

Advanced technology nodes are based on nFET and pFET fins, which are fabricated on the same Silicon level of the wafer. However, in a complimentary FET (CFET) technology the nFET and pFET devices are stacked on top of each other [1]. This provides a significant area reduction mainly driven by a simplified transistor terminal access and the removal of the lateral physical separation between the two transistors. The combination of the CFET with buried power rails can reduce the track height of the cells and the elusive 3 Track standard cell is seen to be a possibility.

Paper Details

Date Published: 20 March 2019
PDF: 12 pages
Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096206 (20 March 2019); doi: 10.1117/12.2514571
Show Author Affiliations
S. M. Y. Sherazi, IMEC (Belgium)
J. K. Chae, IMEC (Belgium)
P. Debacker, IMEC (Belgium)
L. Matti, IMEC (Belgium)
D. Verkest, IMEC (Belgium)
A. Mocuta, IMEC (Belgium)
R. H. Kim, IMEC (Belgium)
A. Spessot, IMEC (Belgium)
A. Dounde, IMEC (Belgium)
J. Ryckaert, IMEC (Belgium)

Published in SPIE Proceedings Vol. 10962:
Design-Process-Technology Co-optimization for Manufacturability XIII
Jason P. Cain, Editor(s)

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