Modern sub-28nm CMOS process nodes, namely FinFET and thin-body silicon-on-insulator have front-end layer thicknesses that are too thin to confine an optical mode. Integration of silicon photonics in these nodes necessitates the development of a deposition process that forms the waveguide structures with sufficient geometries after the CMOS front-end processing. As a step toward creating a photonics process module that can be added to these nodes, we demonstrate the integration of deposited polysilicon photonic platform in a low-power 65nm bulk CMOS process node in a 12” wafer foundry. This process module is designed with minimal number of additional masks to control the fabrication costs by optimizing the fabrication steps and reusing original process’s mask set (~5 additional masks among +40 masks required for the state-of-the-art CMOS nodes). The center of the platform is a polysilicon deposition step, which creates the waveguide layer, followed by a low-temperature crystallization process, which does not impact the electronics. All the passive and active photonic devices are fabricated by patterning and doping this layer. Transistor’s source/drain doping implantations are postponed after finishing and doping photonic polysilicon in order to avoid affecting transistors and reusing the implantation masks for doping active photonic devices as well. The waveguide loss ranges from 10-20dB/cm at 1310nm wavelength. To ease the loss optimization at wafer-scale, deep trench isolation has been added in photonic rows to optically isolate photonics from lossy silicon bulk. Grating couplers are used to couple in/out the light into the chip with 5dB loss. Micro-ring depletion-mode modulators achieved Q-factors of >5k and ~1.6THz free spectral range (FSR) enabling 10 channels in DWDM links. Resonant defect-based photodetectors are utilized on the receive side with 10% quantum efficiency at 5V reverse bias. Our first system demonstrations in this platform are O-band wavelength division multiplexed (WDM) optical transceivers using ring-resonators. Chips are designed in a modular fashion with 64 transceiver macros supporting 4 stand-alone transmit and receive WDM rows each with up to 16 individual channels. Each macro contains about 0.5 million transistors including transceiver’s analog custom front-ends, a digital backend, and microrings’ thermal tuners synthesized by original CMOS technology’s IP standard cells. We have used a variety of available transistor types with different oxide-thicknesses and threshold voltages to optimize energy-efficiency of the electronics. We have characterized the transistor performance across the die and wafer by measuring the frequency of the ring-oscillators embedded in each macro, and observed that the normal distribution is consistent with the foundry provided models for the native CMOS process. Electronics are operating using nominal supply voltage of 1.2V. We achieved 10Gb/s transmission with 4.7dB extinction ratio, and bit-error-rates of below 1e-10 at 7Gb/s with -3dBm sensitivity per channel. Total electrical energy-efficiency is about 600fJ/b (100fJ/b for Tx and 500fJ/b for Rx).

Date Published: 4 March 2019
PDF
Proc. SPIE 10923, Silicon Photonics XIV, 1092302 (4 March 2019); doi: 10.1117/12.2513369

Published in SPIE Proceedings Vol. 10923:
Silicon Photonics XIV
Graham T. Reed; Andrew P. Knights, Editor(s)