Proceedings Paper
Three-step search motion estimation chip for MPEG-2 applications| Format | Member Price | Non-Member Price |
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Paper Abstract
In this paper, a hardware implementation of a 9-PE architecture for three-step search block-matching motion estimation algorithm is proposed. With intelligent data arrangement and memory configuration, the proposed architecture can reach the requirements of low costs, high speed, and low memory bandwidth. With 0.8 micrometer CMOS technology, the proposed chip requires a die size of 6.90 by 5.98 mm and is able to operate at a clock rate more than 50 MHz.
Paper Details
Date Published: 16 September 1996
PDF: 9 pages
Proc. SPIE 2952, Digital Compression Technologies and Systems for Video Communications, (16 September 1996); doi: 10.1117/12.251314
Published in SPIE Proceedings Vol. 2952:
Digital Compression Technologies and Systems for Video Communications
Naohisa Ohta, Editor(s)
PDF: 9 pages
Proc. SPIE 2952, Digital Compression Technologies and Systems for Video Communications, (16 September 1996); doi: 10.1117/12.251314
Show Author Affiliations
Yung-Ping Lee, National Taiwan Univ. (Taiwan)
Chung-Wei Ku, National Taiwan Univ. (Taiwan)
Chung-Wei Ku, National Taiwan Univ. (Taiwan)
Published in SPIE Proceedings Vol. 2952:
Digital Compression Technologies and Systems for Video Communications
Naohisa Ohta, Editor(s)
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