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Proceedings Paper

Design, fabrication, and testing of polysilicon microheaters in silicon
Author(s): Naveen George; Ashok Srivastava
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Paper Abstract

We report the technology for the design, fabrication and testing of polysilicon microheaters in silicon using a standard 2 micrometers n-well CMOS technology. The polysilicon microheaters are realized in two steps: layout design for CMOS process and post processing etching. An additional layer in CMOS technology called `open' was incorporated. The `open' layer creates a direct opening to the substrate. Post processing is done on the fabricated CMOS chips using isotropic etchant like xenon difluoride (XeF2) or anisotropic etchant like ethylenediamine pyrocatechol (EDP) to create a `cavity' in the silicon substrate. The cavity provides thermal isolation from the polysilicon microheaters to the circuits and other devices. These microheaters can reach incandescence at very low power. Several test devices incorporating arrays of polysilicon microheaters were designed and fabricated. Measurements are presented that verify the design and performance of the microheater.

Paper Details

Date Published: 13 September 1996
PDF: 7 pages
Proc. SPIE 2880, Microlithography and Metrology in Micromachining II, (13 September 1996); doi: 10.1117/12.250954
Show Author Affiliations
Naveen George, Alliance Semiconductor (United States)
Ashok Srivastava, Louisiana State Univ. (United States)

Published in SPIE Proceedings Vol. 2880:
Microlithography and Metrology in Micromachining II
Michael T. Postek Jr.; Craig R. Friedrich, Editor(s)

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