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Proceedings Paper

Effect of the pLDD implantation dose on pMOS transistor characteristics
Author(s): Eitan N. Shauly; Richard M. Fastow; Yigal Komem; Itzhak Edrei
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Paper Abstract

pMOS transistors having lightly doped drain (pLDD) structures were fabricated with varying channel lengths and pLDD implantation doses. The effect of the implantation dose on the saturation current, peak substrate current, effective channel length, and threshold voltage was studied. It was found that above a critical pLDD dose (approximately 5 X 1012 B/cm2) the effective channel length was reduced, resulting in an increase in the saturation current and a decrease in the threshold voltage. The peak substrate current, however, decreased with the pLDD implantation does up until a value of 5 X 1013 B/cm2. An empirical relationship between the saturation current and the peak substrate current for transistors of varying channel lengths was derived, and is given as: Ibp equals 1.068 +/- 0.15 * Idp2.232+/- 0.12.

Paper Details

Date Published: 13 September 1996
PDF: 10 pages
Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250890
Show Author Affiliations
Eitan N. Shauly, Tower Semiconductor and Technion-Israel Institute of Technology (Israel)
Richard M. Fastow, Tower Semiconductor (Israel)
Yigal Komem, Technion-Israel Institute of Technology (Israel)
Itzhak Edrei, Tower Semiconductor (Israel)

Published in SPIE Proceedings Vol. 2875:
Microelectronic Device and Multilevel Interconnection Technology II
Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit, Editor(s)

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