Share Email Print

Proceedings Paper

High-performance metal-gate SOI CMOS fabricated by ultraclean low-temperature process technologies
Author(s): Takeo Ushiki; Yuichi Hirano; Hisayuki Shimada; Tadahiro Ohmi
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

The threshold voltages of thin-film fully-depleted Si-on- insulator (FDSOI) nMOS and pMOS have been controlled by employing tantalum (Ta), one of the high-refractory metals, for the gate material. For the low-power application in deep quarter-micron regime, when the supply voltage becomes around 1.0 V, it is necessary that the threshold voltages of SOI MOSFETs, are controlled by the work function of the gate material: Work Function Engineering. It is clear that the mid-gap material instead of the poly-crystalline silicon (poly-Si) for the gate material is effective to control the threshold voltage. The use of the mid-gap material leads to the simplicity for CMOS processes because the same gate material is available for both nMOS and pMOS. Ta, one of the mid-gap material, has low resistivity and excellent durability to wet chemical cleaning. The ultraclean, low- temperature process makes it possible to suppress the reaction between Ta and the gate oxide. The results have shown that Ta-gate FDSOI MOSFET exhibits excellent threshold voltage adjustment in 1.0 V application, even if the gate length is reduced to 0.15 micrometers .

Paper Details

Date Published: 13 September 1996
PDF: 11 pages
Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250865
Show Author Affiliations
Takeo Ushiki, Tohoku Univ. (Japan)
Yuichi Hirano, Tohoku Univ. (Japan)
Hisayuki Shimada, Tohoku Univ. (Japan)
Tadahiro Ohmi, Tohoku Univ. (Japan)

Published in SPIE Proceedings Vol. 2875:
Microelectronic Device and Multilevel Interconnection Technology II
Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit, Editor(s)

© SPIE. Terms of Use
Back to Top