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Proceedings Paper

Device and process integration for a 0.55-um channel length CMOS device
Author(s): Whitson G. Waldo; Ibrahim Turkman; Rickey Brownson
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Paper Abstract

The device and process integration for a 5 V 0.55 micron effective channel length double layer poly, triple layer metal CMOS device is presented. The n-well doping has been optimized to minimize punchthrough currents on PMOS devices. Surface and bulk leakage current components have been analyzed for p-channel Leff and n-well doping variation to evaluate the process latitude. A comparison is made with the n-channel transistor leakage due to drain induced barrier lowering. Yield dependence on threshold voltage is discussed by reviewing the results of a threshold voltage matrix. Weff is recovered with LOCOS isolation using a pre-sacrificial oxide etch and the etch time effect on field threshold voltage is presented. The backend development has stressed process simplicity for low cost manufacturing. Scaling in z has enabled via aspect ratios to stay fixed after the shrink. The effect on sidewall coverage by the via angular geometry is discussed. The metallization process has been improved to aid in better sidewall coverage by the sputtered Al alloy. The consequences of interconnect delay are discussed.

Paper Details

Date Published: 13 September 1996
PDF: 12 pages
Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250858
Show Author Affiliations
Whitson G. Waldo, Motorola (United States)
Ibrahim Turkman, Motorola (United States)
Rickey Brownson, Motorola (United States)

Published in SPIE Proceedings Vol. 2875:
Microelectronic Device and Multilevel Interconnection Technology II
Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit, Editor(s)

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