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Proceedings Paper

High contact resistance heavily doped silicided p+ junctions
Author(s): Michael S. Twiford; F. A. Stevie; E. B. Prather; Morgan J. Thoma; William T. Cochran
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Paper Abstract

Submicron CMOS VLSI wafer product yield problems were correlated with a high p+ contact resistance in an Al/TiN/Ti/TiSi2/Si structure. Electrical measurements of contact resistance kelvin (non-interface) versus (interface) contact test structures were used to isolate the high resistance path. Secondary ion mass spectrometry (SIMS) analysis showed good correlation between the Ti to TiSi2 formation and different anneal conditions. The analysis also showed a strong relationship between TiSi2 formation and p+ surface concentration and junction depth. Deeper boron penetration into the silicon will occur with incomplete silicide penetration. The analytical data showed the changes in processing necessary to eliminate the resistance problem and achieve high dopant surface concentration and the desired junction depth.

Paper Details

Date Published: 12 September 1996
PDF: 7 pages
Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); doi: 10.1117/12.250851
Show Author Affiliations
Michael S. Twiford, Lucent Technologies (United States)
F. A. Stevie, Lucent Technologies (United States)
E. B. Prather, Lucent Technologies (United States)
Morgan J. Thoma, Lucent Technologies (United States)
William T. Cochran, Lucent Technologies (United States)

Published in SPIE Proceedings Vol. 2874:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II
Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann, Editor(s)

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