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Proceedings Paper

Rapid debug of yield and performance bottlenecks within the UltraSPARC-I microprocessor
Author(s): Aswin Mehta; Greg Billus
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Paper Abstract

We have developed a set of analysis tools to accelerate root-cause understanding of any UltraSPARCTM-I microprocessor manufacturing process or design problems encountered on the path to volume manufacturing ramp. We also use these tools to understand root-cause of yield or performance limitations. The custom hardware and software developed to support UltraSPARCTM-I debug is presented, followed by a discussion of our debug methodology. We conclude with an example use of the tools and methods presented to analyze and resolve an actual problem experienced during UltraSPARCTM-I manufacturing start- up.

Paper Details

Date Published: 12 September 1996
PDF: 6 pages
Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); doi: 10.1117/12.250839
Show Author Affiliations
Aswin Mehta, Texas Instruments Inc. (United States)
Greg Billus, Texas Instruments Inc. (United States)


Published in SPIE Proceedings Vol. 2874:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II
Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann, Editor(s)

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