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Proceedings Paper

Improved particle control for high volume semiconductor manufacturing for nanoimprint lithography
Author(s): Tsuyoshi Arai; Yoichi Matsuoka; Hisanobu Azuma
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Paper Abstract

Nanoimprint Lithography (NIL) has been shown to be an effective technique for replication of nano-scale features. The NIL process involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for high volume semiconductor manufacturing. Included on the list are overlay, throughput and defectivity. Imprint lithography, like any lithographic approach requires that defect mechanisms be identified and eliminated in order to consistently yield a device. NIL has defect mechanisms unique to the technology, and they include liquid phase defects, solid phase defects and particle related defects. Especially more troublesome are hard particles on either the mask or wafer surface. Hard particles run the chance of creating a permanent defect in the mask, which cannot be corrected through a mask cleaning process. If Cost of Ownership (CoO) requirements are to be met, it is critical to minimize particle formation and extend mask life. In this work, methods including in-situ particle removal, mask neutralization and resist filtration are discussed in detail. As a result of these methods, along with already developed techniques, particle counts on a wafer were reduced to only 0.0005 pieces per wafer path or a single particle over 2000 wafers, with a next target of 0.0001 pieces per wafer path. Particle adder reduction correlates directly with mask life, and a mask life of 81 lots (about 2000 wafers) is demonstrated. New methods are now under development to further extend mask and reduce cost of ownership. In this work on-tool wafer inspection and mask cleaning methods are also introduced.

Paper Details

Date Published: 12 June 2018
PDF: 8 pages
Proc. SPIE 10807, Photomask Japan 2018: XXV Symposium on Photomask and Next-Generation Lithography Mask Technology, 1080704 (12 June 2018); doi: 10.1117/12.2500482
Show Author Affiliations
Tsuyoshi Arai, Canon Inc. (Japan)
Yoichi Matsuoka, Canon Inc. (Japan)
Hisanobu Azuma, Canon Inc. (Japan)

Published in SPIE Proceedings Vol. 10807:
Photomask Japan 2018: XXV Symposium on Photomask and Next-Generation Lithography Mask Technology
Kiwamu Takehisa, Editor(s)

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